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1/14 xc61f series voltage detectors, delay circuit built-in general description the xc61f series are highly accurate, low power consumpt ion voltage detectors, manufactured using cmos and laser trimming technologies. a delay circuit is built-in to each detector. detect voltage is extremely accurate with minimal temperature drift. both cmos and n-channel open drain ou tput configurations are available. since the delay circuit is built-in, peripherals are unnecessary and high density mounting is possible. a pplications microprocessor reset circuitry memory battery back-up circuits power-on reset circuits power failure detection system battery life and charge voltage monitors delay circuitry typical performance characteristics features highly accurate : 2% low power consumption : 1.0 a(typ.)[ v in =2.0v ] detect voltage range : 1.6v ~ 6.0v in 100mv increments operating voltage range : 0.7v ~ 10.0v detect voltage temperature characteristics : 100ppm/ (typ.) built-in delay circuit : 1ms ~ 50ms 50ms ~ 200ms 80ms ~ 400ms output configuration : n-channel open drain or cmos small packages : sot-23 (250mw) : sot-89 (500mw) : to-92 (300mw) * no parts are available with an accuracy of 1% typical application circuits ambient temperature:ta( ) etr0202_002 release delay time vs. ambient temperature release delay time: t dly (ms)
2/14 xc61f series pin number sot-23 sot-89 to-92 (t) to-92 (l) pin name function 3 2 2 1 v in supply voltage input 2 3 3 2 v ss ground 1 1 1 3 v out output pin configuration pin assignment
3/14 xc61f series designator description symbol description c : cmos output output configuration n : n-ch open drain output : e.g. 2.5v 2 , 5 detect voltage 16 ~ 60 : e.g. 3.8v 3, 8 1 : 50ms ~ 200ms 4 : 80ms ~ 400ms release output delay 5 : 1ms ~ 50ms detect accuracy 2 : within 2.0% m : sot-23 p : sot-89 t : to-92 (standard) package l : to-92 (custom pin configuration) r : embossed tape, standard feed l : embossed tape, reverse feed h : paper type (to-92) device orientation b : bag (to-92) product classification ordering information xc61f ?????? block diagrams (1) cmos output (2) n-channel open drain output
4/14 xc61f series parameter symbol ratings units input voltage v in 12.0 v output current i out 50 ma cmos v ss -0.3 ~ v in + 0.3 output voltage n-ch open drain v out v ss -0.3 ~ 9 v sot-23 250 sot-89 500 power dissipation to-92 pd 300 mw operating temperat ure range topr -30 +85 storage temperature range tstg -40 +125 parameter symbol conditions min. typ. max. units circuit detect voltage v df v df(t) x 0.98 v df(t) v df(t) x 1.02 v hysteresis width v hys v df x 0.02 v df x 0.05 v df x 0.08 v v in = 1.5v - 0.9 2.6 v in = 2.0v - 1.0 3.0 v in = 3.0v - 1.3 3.4 v in = 4.0v - 1.6 3.8 supply current i ss v in = 5.0v - 2.0 4.2 a operating voltage v in v df = 1.6v to 6.0v 0.7 - 10.0 v v in = 1.0v 1.0 2.2 - v in = 2.0v 3.0 7.7 - n-ch v ds =0.5v v in = 3.0v 5.0 10.1 - v in = 4.0v 6.0 11.5 - v in = 5.0v 7.0 13.0 - output current i out p-ch v ds =2.1v (cmos output) v in = 8.0v - -10.0 -2.0 ma cmos output - 0.01 - leak current nch open drain ileak v in = 10.0v v out = 10.0v - 0.01 0.1 a detect voltage temperature characteristics v df topr ? v df - 100 - ppm/ - 50 - 200 80 400 release delay time (v dr v out inversion) t dly v in changes from 0.6v to 10v 1 50 ms electrical characteristics v df (t): setting detect voltage value release voltage: v dr = v df + v hys * release delay time: 1ms to 50ms & 80ms to 400ms versions are also available. note: the power consumption during power-start to output being stable (release operation) is 2 a greater than it is after that period (completion of release operation) bec ause of delay circuit through current. ta = 2 5
5/14 xc61f series operational explanation cmos output when a voltage higher than the release voltage (v dr ) is applied to the voltage input pin (vi n ), the voltage will gradually fall. when a voltage higher than the detect voltage (v df ) is applied to vin, output (v out ) will be equal to the input at v in . note that high impedance exists at v out with the n-channel open drain confi guration. if the pin is pulled up, v out will be equal to the pull up voltage. when v in falls below v df , v out will be equal to the ground voltage (v ss ) level (detect state). note that this also applies to n-channel open drain configurations. when vi n falls to a level below that of the minimum operating voltage (v min ) output will become unstable. because the output pin is generally pulled up with n-channel open drai n configurations, output will be equal to pull up voltage. when v in rises above the v ss level (excepting levels lower than minimum operating voltage), v out will be equal to v ss until v in reaches the v dr level. although v in will rise to a level higher than v dr , v out maintains ground voltage level via the delay circuit. following transient delay time, v in will be output at v out . note that high impedance exists with the n-channel open drain configuration and that volt age will be dependent on pull up. timing chart notes: 1. the difference between v dr and v df represents the hysteresis range. 2. release delay time ( t dly ) represents the time it takes for v in to appear at v out once the said voltage has exceeded the v dr level. (t dly )
6/14 xc61f series directions for use notes on use 1. please use this ic within the stated maximum ratings. t he ic is liable to malfunction should the ratings be exceeded. 2. when a resistor is connected between the v in pin and the input with cmos output configurations, oscillation may occur as a result of voltage drops at r in if load current (i out ) exists. it is therefore re commend that no resistor be added. (refer to oscillation description (1) below) 3. when a resistor is connected between the v in pin and the input with cmos output c onfigurations, irrespective of n-ch output configurations, oscillati on may occur as a result of through current at the time of voltage release even if load current (i out ) does not exist. (refer to oscillation description (2) below) 4. with a resistor connected between the v in pin and the input, detect and release voltage will rise as a result of the ic's supply current flowing through the v in pin. 5. if a resistor (r in ) must be used, then please use with as small a level of input impedance as possible in order to control the occurrences of oscillation as described above. further, please ensure that r in is less than 10k and that c in is more than 0.1 f (figure 1). in such cases, detect and release voltages will rise due to voltage drops at r in brought about by the ic's supply current. oscillation description (1) oscillation as a result of output cu rrent with the cmos output configuration: when the voltage applied at in rises, release operat ions commence and the detector' s output voltage increases. load current (i out ) will flow through r l . because a voltage drop (r in x i out ) is produced at the r in resistor, located between the input (in) and the v in pin, the load current will flow via the ic's v in pin. the voltage drop will also lead to a fall in the voltage level at the v in pin. when the v in pin voltage level falls below the detect voltage level, detect operations will commence. following det ect operations, load current flow will cease and since voltage drop at r in will disappear, the voltage level at the v in pin will rise and release operations will begin over again. oscillation may occur with this " release - detect - release " repetition. further, this condition will also appear via means of a similar mechanism during detect operations. (2) oscillation as a result of through current: since the xc61f series are cmos ic s , through current will flow when the ic's internal circuit switching operates (during release and detect operations). consequently, oscillation is liable to occur during release voltage operations as a result of output current which is in fluenced by this through current (figure 3). since hysteresis exists during detect op erations, oscillation is unlikely to occur. figure 1. when using an input resistor
7/14 xc61f series directions for use (continued) oscillation description (continued)
8/14 xc61f series y y y y y * cmos?????? 220k 220k * test circuits *not necessary with cmos output products. circuit circuit circuit circuit circuit
9/14 xc61f series typical performance characteristics
10/14 xc61f series typical performance characteristics (continued) release delay time: t dly (ms) release delay time: t dly (ms) release delay time: t dly (ms) ( 7 ) release dela y time vs. ambient tem p erature
11/14 xc61f series typical performance characteristics (continued) release delay time: t dly (ms) ( 8 ) release dela y time vs. in p ut volta g e
12/14 xc61f series packaging information sot-23 sot-89 to-92
13/14 xc61f series f 6 1 123 mark configuration voltage (v) a cmos 0.x b cmos 1.x c cmos 2.x d cmos 3.x e cmos 4.x f cmos 5.x h cmos 6.x n-channel open drain (xc61fn series) mark configuration voltage (v) k n-ch 0.x l n-ch 1.x m n-ch 2.x n n-ch 3.x p n-ch 4.x r n-ch 5.x s n-ch 6.x mark voltage (v) mark voltage (v) 0 x.0 5 x.5 1 x.1 6 x.6 2 x.2 7 x.7 3 x.3 8 x.8 4 x.4 9 x.9 voltage (v) delay time 5 50 ~ 200ms 6 80 ~ 400ms 7 1 ~ 50ms mark output configuration c cmos n n-ch mark voltage (v) 3 3 3.3 5 0 5.0 mark delay time 1 50ms ~ 200ms 4 80ms ~ 400ms 5 1ms ~ 50ms mark detect voltage accuracy 2 within + 2% mark production year 3 2003 4 2004 marking rule represents integer of detect vo ltage and output configuration cmos output (xc61fc series) represents decimal number of detect voltage represents delay time represents assembly lot number (based on internal standards) to-92 represents output configuration , represents detect voltage represents delay time represents detect voltage accuracy represents a least significant digi t of the production year (ex.) represents production lot number 0 to 9, a to z repeated (g, i, j, o, q, w expected) 12 3 123 to-92 (l type) top view to-92 (t type) top view
14/14 xc61f series 1. the products and product specifications cont ained herein are subject to change without notice to improve performance characteristic s. consult us, or our representatives before use, to confirm that the inform ation in this catalog is up to date. 2. we assume no responsibility for any infri ngement of patents, pat ent rights, or other rights arising from the use of any info rmation and circuitry in this catalog. 3. please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this catalog. 4. the products in this catalog are not developed, designed, or approved for use with such equipment whose failure of malfunction ca n be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. atomic energy; aerospace; transpor t; combustion and associated safety equipment thereof.) 5. please use the products listed in this catalog within the specified ranges. should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. we assume no responsibility for damage or loss due to abnormal use. 7. all rights reserved. no part of this ca talog may be copied or reproduced without the prior permission of torex semiconductor ltd.

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